MUX 8 to 1 Code

MUX 2 t0 1

module MUX2To1 (i0, i1, s, Out);

input i0, i1;

input s;

output Out;

wire and0_out, and1_out;

wire not0_out;

and a0 (and0_out, i0, not0_out );

and a1 (and1_out, i1, s  );

not n0 (not0_out, s);

or o1  (Out, and0_out, and1_out);

endmodule

MUX 4 t0 1

module MUX4To1 (I0, I1, I2, I3, S0, S1, Out);

input I0, I1, I2, I3;

input S0, S1;

output Out;

wire and0_out, and1_out, and2_out, and3_out;

wire not0_out, not1_out;

and a0 (and0_out, I0, not0_out, not1_out  );

and a1 (and1_out, I1, S0, not1_out  );

and a2 (and2_out, I2, not0_out, S1  );

and a3 (and3_out, I3, S0, S1  );

not n0 (not0_out, S0);

not n1 (not1_out, S1);

or o1  (Out, and0_out, and1_out, and2_out, and3_out);

endmodule

MUX 8 to 1

module MUX8To1 (Out, I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2);

input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2;

output Out;

wire y0, y1;

MUX4To1 MUX_0 (I0, I1, I2, I3, S0, S1, y0);

MUX4To1 MUX_1 (I4, I5, I6, I7, S0, S1, y1);

MUX2To1 MUX_2 (y0, y1, S2, Out);

Endmodule

Test Bench

module TestBench_Mux8To1;

reg i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;

wire out;

MUX8To1 inst_Mux8 (out, i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2);

initial

                begin

                                #5 i0=0;i1=0;i2=0;i3=0;s0=0;s1=0;

                                #5 i0=1;

                                #5 i1=0;

                                #5 i2=0;

                                #5 i3=0;

                                #5 s0=0; s1=0;

                                #5 s0=1; s1=0;

                                #5 s0=0; s1=1;

                                #5 s0=1; s1=1;

                               

                                #5 i0=0;

                                #5 i1=1;

                                #5 i2=0;

                                #5 i3=0;

                                #5 s0=0; s1=0;

                                #5 s0=1; s1=0;

                                #5 s0=0; s1=1;

                                #5 s0=1; s1=1;

               

                                #5 i0=0;

                                #5 i1=0;

                                #5 i2=1;

                                #5 i3=0;

                                #5 s0=0; s1=0;

                                #5 s0=1; s1=0;

                                #5 s0=0; s1=1;

                                #5 s0=1; s1=1;

                               

                                #5 i0=0;

                                #5 i1=0;

                                #5 i2=0;

                                #5 i3=1;

                                #5 s0=0; s1=0;

                                #5 s0=1; s1=0;

                                #5 s0=0; s1=1;

                                #5 s0=1; s1=1;

               

               

                end

               

initial

                $monitor ( " I0= %b, I1= %b, I2= %b, I3=%b, S0=%b, S1=%b, Out=%b", i0,i1,i2,i3,s0,s1,out);

endmodule